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HD74LV166A
Parallel-Load 8-bit Shift Register
ADE-205-268 (Z) 1st Edition March 1999 Description
The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is asynchronous and active-low. The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features
* * * * * * VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25C) Output current 6 mA (@VCC = 3.0 V to 3.6 V), 12 mA (@VCC = 4.5 V to 5.5 V)
HD74LV166A
Function Table
Inputs CLR L H H H H H SH/LD X X L H H X CLK INH X L L L L H CLK X L SER X X X H L X A ... H X X a ... h X X X Internal outputs QA L QA0 a H L QA0 QB L QB0 b QAn QAn QB0 Output QH L QH0 h QGn QGn QH0
Note: H: High level L: Low level : Low to high transition X: Immaterial a ... h: Parallel data QA0 ... Q H0: Outputs remain unchanged. QAn ... Q Gn : Data shifted from the previous stage on a positive edge at the clock input.
Pin Arrangement
SER 1 A2 B3 C4 D5 CLK INH 6 CLK 7 GND 8
16 VCC 15 SH/LD 14 H 13 QH 12 G 11 F 10 E 9 CLR
(Top view)
2
HD74LV166A
Absolute Maximum Ratings
Item Supply voltage range Input voltage range*
1 1, 2
Symbol VCC VI VO
Ratings -0.5 to 7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to 7.0
Unit V V V
Conditions
Output voltage range*
Output: H or L VCC: OFF
Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at Ta = 25C (in still air)*3
I IK I OK IO I CC or IGND PT
-20 50 25 50 785 500
mA mA mA mA mW
VI < 0 VO < 0 or VO > VCC VO = 0 to VCC
SOP TSSOP
Storage temperature
Tstg
-65 to 150
C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150C.
3
HD74LV166A
Recommended Operating Conditions
Item Supply voltage range Input voltage range Output voltage range Output current Symbol VCC VI VO I OH Min 2.0 0 0 -- -- -- -- I OL -- -- -- -- Input transition rise or fall rate t /v 0 0 0 Operating free-air temperature Ta -40 Max 5.5 5.5 VCC -50 -2 -6 -12 50 2 6 12 200 100 20 85 C ns/V A mA Unit V V V A mA H or L VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V Conditions
Note: Unused or floating inputs must be held high or low.
4
HD74LV166A
Logic Diagram
A SER B C D E F G CLR H SH/LD CLK CLK INH
R CP S CD Q
R CP S Q CD
QH
5
HD74LV166A
Timing Diagram
CLK CLK INH CLR SER SH/LD
A B C D E F G H H L H L H L H H H H L H L H L H L
Parallel Inputs
Output QH
Serial shift Clear Load Inhibit
Serial shift
6
HD74LV166A
DC Electrical Characteristics
* Ta = -40 to 85C
Item Input voltage Symbol VIH VCC (V)* 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 VIL 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Output voltage VOH Min to Max 2.3 3.0 4.5 VOL Min to Max 2.3 3.0 4.5 Input current Quiescent supply current Output leakage current Input capacitance IIN ICC IOFF CIN 0 to 5.5 5.5 0 3.3 Min 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 -- -- -- -- VCC - 0.1 2.0 2.48 3.8 -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.7 Max -- -- -- -- 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 -- -- -- -- 0.1 0.4 0.44 0.55 1 20 5 -- A A A pF Unit V Test Conditions
V
IOL = -50 A IOL = -2 mA IOL = -6 mA IOL = -12 mA IOL = 50 A IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = 5.5 V or GND VI = VCC or GND, IO = 0 VI or VO = 0 V to 5.5 V VI = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
7
HD74LV166A
Switching Characteristics
* VCC = 2.5 0.2 V
Ta = 25C Item Maximum clock frequency Symbol fmax Min 50 Typ 80 Max -- Ta = -40 to 85C Min 45 Max -- Unit MHz Test Conditions CL = 15 pF FROM (Input) TO (Output)
40 Propagation delay time tPLH/tPHL --
65 12.2
-- 19.8
35 1.0
-- 22.0 ns
CL = 50 pF CL = 15 pF CLK QH
-- tPHL -- -- Setup time tsu 7.0 6.5 7.0 8.5 Hold time th -0.5 -0.5 -0.5 Pulse width tw 8.0 8.5
15.3 10.8 14.2 -- -- -- -- -- -- -- -- --
23.3 16.0 19.5 -- -- -- -- -- -- -- -- --
1.0 1.0 1.0 7.0 8.5 8.5 9.5 0.0 0.0 0.0 9.0 9.0
26.0 18.0 22.0 -- -- -- -- -- -- -- -- -- ns ns ns ns
CL = 50 pF CL = 15 pF CL = 50 pF CLK INH before CLK Data before CLK SH/LD high before CLK SER before CLK PAR data after SH/LD SER data after CLK SH/LD high after CLK CLR low CLK H or L CLR
8
HD74LV166A
Switching Characteristics (cont)
* VCC = 3.3 0.3 V
Ta = 25C Item Maximum clock frequency Symbol fmax Min 65 Typ 115 Max -- Ta = -40 to 85C Min 55 Max -- Unit MHz Test Conditions CL = 15 pF FROM (Input) TO (Output)
60 Propagation delay time tPLH/tPHL --
90 8.6
-- 15.4
50 1.0
-- 18.0 ns
CL = 50 pF CL = 15 pF CLK QH
-- tPHL -- -- Setup time tsu 5.0 5.0 5.0 5.0 Hold time th 0.0 0.0 0.0 Pulse width tw 6.0 6.0
10.9 7.9 10.4 -- -- -- -- -- -- -- -- --
18.9 12.5 16.3 -- -- -- -- -- -- -- -- --
1.0 1.0 1.0 5.0 6.0 6.0 6.0 0.0 0.0 0.0 7.0 7.0
21.5 15.0 18.5 -- -- -- -- -- -- -- -- -- ns ns ns ns
CL = 50 pF CL = 15 pF CL = 50 pF CLK INH before CLK Data before CLK SH/LD high before CLK SER before CLK PAR data after SH/LD SER data after CLK SH/LD high after CLK CLR low CLK H or L CLR
9
HD74LV166A
Switching Characteristics (cont)
* VCC = 5.0 0.5 V
Ta = 25C Item Maximum clock frequency Symbol fmax Min 110 Typ 165 Max -- Ta = -40 to 85C Min 90 Max -- Unit MHz Test Conditions CL = 15 pF FROM (Input) TO (Output)
95 Propagation delay time tPLH/tPHL --
125 6.0
-- 9.9
85 1.0
-- 11.5 ns
CL = 50 pF CL = 15 pF CLK QH
-- tPHL -- -- Setup time tsu 3.5 4.5 4.0 4.0 Hold time th 1.0 1.0 1.0 Pulse width tw 5.0 4.0
7.7 5.4 6.9 -- -- -- -- -- -- -- -- --
11.9 8.6 10.6 -- -- -- -- -- -- -- -- --
1.0 1.0 1.0 3.5 4.5 4.0 4.0 1.0 1.0 1.0 5.0 4.0
13.5 10.0 12.0 -- -- -- -- -- -- -- -- -- ns ns ns ns
CL = 50 pF CL = 15 pF CL = 50 pF CLK INH before CLK Data before CLK SH/LD high before CLK SER before CLK PAR data after SH/LD SER data after CLK SH/LD high after CLK CLR low CLK H or L CLR
10
HD74LV166A
Operating Characteristics
* CL = 50 pF
Ta = 25C Item Power dissipation capacitance Symbol CPD VCC (V) 3.3 Min -- Typ 36.1 Max -- Unit pF Test Conditions f = 10 MHz
5.0
--
37.5
--
Test Circuit
Measurement point
CL*
Note: C L includes the probe and jig capacitance.
11
HD74LV166A
Waveform
tW VCC CLR
50%VCC 50%VCC
tn CLK
50%VCC 50%VCC
tn+1
tn
tn+1
0V VCC
50%VCC
50%VCC
tW tsu Data
50%VCC
0V th
50%VCC 50%VCC
tsu
th VCC
50%VCC
0V tPHL Output QH
50%VCC
tPHL
50%VCC
tPHL VOH
50%VCC
VOL
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , t r 3 ns, t f 3 ns 2. The output are measured one at a time with one transition per measurement.
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HD74LV166A
Package Dimensions
10.06 10.5 Max 16 9
5.5
1
0.22 0.05 0.20 0.04
8 0.80 Max
2.20 Max
0.20 7.80 + 0.30 -
1.15 0 - 8 0.70 0.20
1.27
0.42 0.08 0.40 0.06
0.12 M
Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DA -- Conforms 0.24 g
0.10 0.10
0.15
13
HD74LV166A
Unit: mm
9.9 10.3 Max 16 9 3.95 1 1.27 0.635 Max 8
0.11 0.14 + 0.04 - 1.75 Max
*0.22 0.03 0.20 0.03
0.10 6.10 + 0.30 -
1.08 0 - 8
+ 0.67 0.60 - 0.20
*0.42 0.08 0.40 0.06
0.15 0.25 M
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
FP-16DN Conforms Conforms 0.15 g
14
HD74LV166A
5.0 5.3 Max 16 9 4.40 1
0.08 0.22 + 0.07 -
8 0.65 1.0 6.40 0.20 0 - 8 0.50 0.10
0.20 0.06
0.13 M 0.65 Max 0.17 0.05 0.15 0.04
1.10 Max
0.10
0.07 +0.03 -0.04
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TTP-16DA -- -- 0.05 g
15
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
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Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.

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